What is claimed

Google is reported to be working with AMD on its 10th-generation TPU family. The scope of the collaboration is not yet known, but AMD's role in the project is thought to differ from conventional TPU design.

The reason lies in Google's existing arrangement. The company has developed its own TPU accelerators for nine generations and works with Broadcom on the physical design of the chips. Because of that established relationship, AMD directly designing the TPU v10i inference or v10t training chip is seen as unlikely.

The more plausible scenario is a contribution in specific areas:

  • CPU intellectual property,
  • advanced packaging,
  • interconnect technologies,
  • programmable logic.

The real story: CPUs in the package

What SemiAnalysis highlights is not the collaboration itself but that Google is weighing adding CPU cores to the TPU package.

The technical reason is a change in workloads. Reinforcement learning, reasoning and agent-based AI workloads can require more general-purpose compute than conventional AI training. The model is not only doing matrix multiplication; it calls tools, reads results and makes branching decisions. Those are areas where the CPU, not the accelerator, is strong.

Google's current hardware points the same way: its TPU 8i systems use one Axion CPU for every two TPUs. General-purpose compute is already being added to the system; the question is where to put it.

Why in the same package?

Placing CPU cores directly in the TPU package shortens the communication distance between the CPU and the AI accelerators. That can raise performance and lower power consumption at the same time. Data moves within the package instead of travelling long paths across a board.

AMD has concrete experience here: in its Instinct MI300A it combined x86 CPU and accelerator dies in the same package. That background is what makes the collaboration claim technically coherent.

How to read it

The caveat is plain: this is at the level of a claim, with no confirmed statement from either party and no known scope. Everything about AMD's role is inference at this stage.

Even unconfirmed, though, it points to a meaningful trend. AI hardware was long debated around a single question: how many operations per second. As agent workloads spread, the question changes; how close the general-purpose processor feeding the accelerator sits now matters alongside how fast the accelerator is. That Google builds its own chip makes trying an architectural change like this easier — it is not bound by the limits of an off-the-shelf product.